The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory.
Conventional memory architectures include features that waste DC and AC current consumption by one or more of the following (i) passive (no gain) static loads, (ii) large sub-wordlines, (iii) sub-wordline circuits not included in the memory array, (iv) row, column and block array partitions not included in the memory array, (v) double ended buses (address path, local and global data output path, data input path), (vi) equalization circuitry placed at one end of the memory array, (vii) address predecoders, and/or (viii) replaced defective blocks still connected to the source current.
The present invention concerns a memory array comprising at least 2 Meg of SRAM cells and configured to consume a maximum average operating current of 9.43 mA.
The objects, features and advantages of the present invention include providing a memory that may (i) reduce and/or eliminate DC current consumption, (ii) minimize rail-to-rail switching capacitance, (iii) reduce the amount of rail-to-rail switching, and/or (iv) reduce AC current consumption,